library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity alu is
    port(
    a, b: in std_logic_vector(31 downto 0);
    alucontrol: in std_logic_vector(2 downto 0);
    result: out std_logic_vector(31 downto 0);
    zero: out std_logic
    );
end alu;

architecture behav of alu is
    signal result_s: std_logic_vector(31 downto 0);
begin
    result_s <=
        a and b
            when alucontrol = "000" else
        a or b
            when alucontrol = "001" else
        a + b
            when alucontrol = "010" else
        a and not(b)
            when alucontrol = "100" else
        a or not(b)
            when alucontrol = "101" else
        a - b
            when alucontrol = "110" else
        conv_std_logic_vector(1, 32)
            when alucontrol = "111" and a < b else
        conv_std_logic_vector(0, 32)
            when alucontrol = "111" and a >= b else
        (others => '-');

    result <= result_s;

    zero <=
        '1' when result_s = conv_std_logic_vector(0, 32) else
        '0';
end behav;
